Compiling the language Balsa to delay insensitive hardware
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
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We present a new CAD tool set for generating asynchronous circuits from high-level Verilog level-sensitive specifications. Initially high-level Verilog descriptions are compiled and converted into a novel intermediate Petri-net format. The intermediate format is subsequently passed to optimization tools and mapping tools where it is directly mapped into asynchronous datapath and control circuits using David Cells (DCs). Finally logic optimization tools are applied to generate speed independent (SI) circuits. The speed independent circuits generated perform well compared to circuits generated by existing asynchronous tools.