Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Low power, high speed, and reduced cost requirements force integration of specialized Intellectual Property (IP) like complex I/O blocks on a System on Chip (SoC). Today designers have access to a variety of specialized IP blocks and cells for use in SoC design flows. Complex I/O appear in a myriad of standards such as USB 1.0/1.1/2.0, IEEE 1394 a/b (FireWire), SSTL, HSTL, PCI-X, LVDS, and more. These new standards are driven by consumer's demand for bandwidth and capability, and the industry's desire to reuse proven design blocks in vastly different applications and domains [1]. Integration of these specialized IP blocks introduces increased complexity to design flows. For example, digital designs must now consider the analog like properties of some complex I/O. This paper discusses the uniqueness of embedding complex I/O in a SoC. The features and properties that differentiate complex I/O from standard design practices will be described. Finally methodologies for characterizing and building accurate digital abstractions of I/O will be presented.