A new page table for 64-bit address spaces
SOSP '95 Proceedings of the fifteenth ACM symposium on Operating systems principles
| Hi-index | 0.00 |
Modern operating systems provide a rich set of interfaces for mapping, sharing, and protecting memory. Different memory management unit (MMU) architectures provide different mechanisms for managing memory translations. Since the same OS usually runs on different MMU architectures, a software "hardware address translation" (hat) layer that abstracts the MMU architecture is normally implemented between MMU hardware and the virtual memory system of the OS. In this paper, we study the impact of the OS and the MMU on the structure and performance of the hat layer. In particular, we concentrate on the role of the hat layer on the scalability of system performance on symmetric multiprocessors with 2-12 CPUs. The results show that, unlike single-user applications, multi-user applications require very careful multi-threading of the hat layer to achieve system performance that scales with the number of CPUs. In addition, multi-threading the hat can result in better performance in lesser amounts of physical memory.