SoC design of Ogg Vorbis decoder using embedded processor

Authors:
Atsushi Kosaka;Satoshi Yamaguchi;Hiroyuki Okuhata;Takao Onoye;Isao Shirakawa
Affiliations:
Osaka University, Osaka, Japan;Osaka University, Osaka, Japan;Synthesis Corporation, Osaka, Japan;Osaka University, Osaka, Japan;Osaka University, Osaka, Japan
Venue:
Proceedings of the 1st conference on Computing frontiers
Year:
2004

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Abstract

This paper presents an ARM-based SoC architecture for the Ogg Vorbis audio decoder. A trivial software-based implementation incurs high computational cost and requires high operation frequency. In order to achieve realtime processing and efficient bus interface design for our target system, the load of an embedded processor is reduced through the use of specific hardware for a functional block that has higher computational complexity than other blocks of Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) is detected as the most computation-intensive functional block. As a result of FPGA (Field Programmable Gate Array) implementation, a 48% improvement in execution cycle is achieved by the specific hardware with 3,749 slices.