Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis

Authors:
Khushwinder Jasrotia;Jianwen Zhu
Affiliations:
-;-
Venue:
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Year:
2004

Citing 0
Cited 2

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Abstract

In this paper, we argue that the classic micro-architecture model, namely finite state machine with datapath (FSMD), cannot handle procedure abstraction needed by complex applications. This presents one of the major obstacles for the adoption of high-level synthesis technology inpractice. We propose a simple extension of FSMD, called stacked FSMD, which mimics the procedure linkage concepts in software. We demonstrate that the new micro-architecture can not only fully support procedure calls, but also be made power efficient by a technique called region-based partitioning, which can be applied directly at the behavioral level with the assistance of simple metric evaluated at the behavioral level. With a rigorous experimental procedure, we show that the controller power saving achieved can range from 12% to 68% with modest overhead in area.