Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach

  • Authors:

  • Henry H. Y. Chan;Zeljko Zilic

  • Affiliations:

  • -;-

  • Venue:
  • ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
  • Year:
  • 2004

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Abstract

On-chip phase-locked loops (PLLs) are critical components for clock generation and recovery in high-speed communication and data processing systems. The presence of partially-correlated substrate noise presents a new challenge to predicting PLL jitter. We propose a model that describes the substrate noise-to-jitter transfer characteristics for CMOS ring oscillator-based PLLs on epitaxial substrate. The proposed model is verified against jittersimulations.