Proceedings of the Conference on Design, Automation and Test in Europe
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Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and realtime systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in such systems. The scheme uses internal Performance Monitoring features and an external watchdog processor (WDP). The Performance Monitoring features enable counting the number of committed instructions in aprogram. The scheme is experimentally evaluated on a 32-bit Pentium® processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into the Pentium® processor. The results show that the error detection coverage varies between to90.92% and 98.41%, for different workloads.