Design of a nanosensor array architecture

  • Authors:

  • Wei Xu;N. Vijaykrishnan;Y. Xie;M. J. Irwin

  • Affiliations:

  • The Pennsylvania State University, University Park, PA;The Pennsylvania State University, University Park, PA;The Pennsylvania State University, University Park, PA;The Pennsylvania State University, University Park, PA

  • Venue:
  • Proceedings of the 14th ACM Great Lakes symposium on VLSI
  • Year:
  • 2004

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Abstract

This paper describes a nanowire sensor array architecture for high-speed, high-accuracy sensor systems. The chip has very simple processing elements (PEs) in a massively parallel architecture, in which each PE is directly connected to seven sensors. A sampling rate of 100 ns is enough to realized high-speed sensing feedback for electronic nose. We aim to create a very simple architecture, because a compact design is required ton integrate as many PEs as possible on a single chip. A widely used, easy to implement estimator-minimum distance classifier is introduced to realize the pattern recognition. A sample design is implemented in VHDL and has been simulated and synthesized using TSMC 0.25 standard cell library and a commercial 0.16 standard cell library.