High-level power analysis for on-chip networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
A Memory-Effective Routing Strategy for Regular Interconnection Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Microarchitecture of a High-Radix Router
Proceedings of the 32nd annual international symposium on Computer Architecture
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Traffic generation and performance evaluation for mesh-based NoCs
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Hardware-modulated parallelism in chip multiprocessors
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
The BlackWidow High-Radix Clos Network
Proceedings of the 33rd annual international symposium on Computer Architecture
Journal of Parallel and Distributed Computing
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
FIR: an efficient routing strategy for tori and meshes
Journal of Parallel and Distributed Computing - 19th International parallel and distributed processing symposium
Throughput fairness in k-ary n-cube networks
ACSC '06 Proceedings of the 29th Australasian Computer Science Conference - Volume 48
Analytical Modeling of Communication Latency in Multi-Cluster Systems
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 2
Resource allocation and cross-layer control in wireless networks
Foundations and Trends® in Networking
Increasing the throughput of an adaptive router in network-on-chip (NoC)
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips
IEEE Transactions on Parallel and Distributed Systems
Adaptive routing in high-radix clos network
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Towards a formal theory of on chip communications in the ACL2 logic
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
A performance model for analysis of heterogeneous multi-cluster systems
Parallel Computing
Performance comparison of routing algorithms in wormhole-switched networks
Parallel Computing
Characterization of spatial fault patterns in interconnection networks
Parallel Computing
Analytical modeling of interconnection networks in heterogeneous multi-cluster systems
The Journal of Supercomputing
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analytical communication networks model for enterprise Grid computing
Future Generation Computer Systems
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
Interconnect design considerations for large NUCA caches
Proceedings of the 34th annual international symposium on Computer architecture
Architecture of the Scalable Communications Core
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Power and Energy Exploration of Network-on-Chip Architectures
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
The Data Vortex, an All Optical Path Multicomputer Interconnection Network
IEEE Transactions on Parallel and Distributed Systems
Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks
IEEE Transactions on Parallel and Distributed Systems
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Communication network analysis of the enterprise grid systems
ACSW '07 Proceedings of the fifth Australasian symposium on ACSW frontiers - Volume 68
Layered switching for networks on chip
Proceedings of the 44th annual Design Automation Conference
Multicasting based topology generation and core mapping for a power efficient networks-on-chip
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Performance analysis of fault-tolerant routing algorithm in wormhole-switched interconnections
The Journal of Supercomputing
Quasi-global routing for fault-tolerant high-performance interconnection networks
PDCN'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: parallel and distributed computing and networks
Communication delay analysis of fault-tolerant pipelined circuit switching in torus
Journal of Computer and System Sciences
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The AMD Opteron Northbridge Architecture
IEEE Micro
A New Cost-Effective Technique for QoS Support in Clusters
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Arithmetic on a distributed-memory quantum multicomputer
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Run-time power gating of on-chip routers using look-ahead routing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Design issues in next-generation merchant switch fabrics
IEEE/ACM Transactions on Networking (TON)
Diameter variability of cycles and tori
Information Sciences: an International Journal
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology-Driven, Highly-Scalable Dragonfly Topology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
An evolutionary design technique for collective communications on optimal diameter-degree networks
Proceedings of the 10th annual conference on Genetic and evolutionary computation
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Proceedings of the 45th annual Design Automation Conference
Journal of Discrete Algorithms
Proceedings of the ACM workshop on Programmable routers for extensible services of tomorrow
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Statistical Approach to NoC Design
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Reducing the Interconnection Network Cost of Chip Multiprocessors
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs
Proceedings of the conference on Design, automation and test in Europe
Performance modeling and analysis of heterogeneous meta-computing systems interconnection networks
Computers and Electrical Engineering
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Distributed flit-buffer flow control for networks-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A new modelling approach of wormhole-switched networks with finite buffers
International Journal of Parallel, Emergent and Distributed Systems
Unicast-based fault-tolerant multicasting in wormhole-routed hypercubes
Journal of Systems Architecture: the EUROMICRO Journal
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Communication Based Proactive Link Power Management
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Diastolic arrays: throughput-driven reconfigurable computing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Analysis of communication delay bounds for network on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Token tenure: PATCHing token counting using directory-based cache coherence
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Adaptive data compression for high-performance low-power on-chip networks
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Power reduction of CMP communication networks via RF-interconnects
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Multicast routing with dynamic packet fragmentation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Router with centralized buffer for network-on-chip
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
Multi-cluster computing interconnection network performance modeling and analysis
Future Generation Computer Systems
Understanding the interconnection network of SpiNNaker
Proceedings of the 23rd international conference on Supercomputing
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Application-aware deadlock-free oblivious routing
Proceedings of the 36th annual international symposium on Computer architecture
Indirect adaptive routing on large scale interconnection networks
Proceedings of the 36th annual international symposium on Computer architecture
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
Achieving predictable performance through better memory controller placement in many-core CMPs
Proceedings of the 36th annual international symposium on Computer architecture
Design and performance of speculative flow control for high-radix datacenter interconnect switches
Journal of Parallel and Distributed Computing
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Evolutionary optimization of multistage interconnection networks performance
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
Honeycomb-structured computational interconnects and their scalable extension to spherical domains
Proceedings of the 11th international workshop on System level interconnect prediction
VL2: a scalable and flexible data center network
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
A high-performance low-power nanophotonic on-chip network
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A variable frequency link for a power-aware network-on-chip (NoC)
Integration, the VLSI Journal
Analysis of photonic networks for a chip multiprocessor using scientific applications
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Static virtual channel allocation in oblivious routing
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Flow-aware allocation for on-chip networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
CTC: An end-to-end flow control protocol for multi-core systems-on-chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Scalability of network-on-chip communication architecture for 3-D meshes
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring concentration and channel slicing in on-chip network router
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Adding mechanisms for QoS to a network-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Computers and Electrical Engineering
A DP-network for optimal dynamic routing in network-on-chip
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Supporting RTL flow compatibility in a microarchitecture-level design framework
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
RouteBricks: exploiting parallelism to scale software routers
Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles
An SDRAM-aware router for Networks-on-Chip
Proceedings of the 46th Annual Design Automation Conference
Formal validation of deadlock prevention in networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Interconnection network simulation using traces of MPI applications
International Journal of Parallel Programming
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Router microarchitecture and scalability of ring topology in on-chip networks
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Path-based, randomized, oblivious, minimal routing
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Segment gating for static energy reduction in Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures
Computers and Electrical Engineering
Router designs for elastic buffer on-chip networks
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
HyperX: topology, routing, and packaging of efficient large-scale networks
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Allocator implementations for network-on-chip routers
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new ultra-low latency message transfer mechanism
CSN '07 Proceedings of the Sixth IASTED International Conference on Communication Systems and Networks
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
In-network coherence filtering: snoopy coherence without broadcasts
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Application-aware prioritization mechanisms for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Productive petascale computing: requirements, hardware, and software
Productive petascale computing: requirements, hardware, and software
A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
ACM Transactions on Embedded Computing Systems (TECS)
A performance analysis framework for routing lookup in scalable routers
ICOIN'09 Proceedings of the 23rd international conference on Information Networking
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mesh-based many-core performance under process variations: a core yield perspective
ACM SIGARCH Computer Architecture News
Analytical modelling of networks in multicomputer systems under bursty and batch arrival traffic
The Journal of Supercomputing
Flexible architectural support for fine-grain scheduling
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Reducing complexity in tree-like computer interconnection networks
Parallel Computing
Leakage-saving opportunities in mesh-based massive multi-core architectures
ACM SIGARCH Computer Architecture News
Performance analysis of interconnection networks under bursty and batch arrival traffic
ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing
Cross-line: a globally adaptive control method of interconnection network
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
rHALB: a new load-balanced routing algorithm for k-ary n-cube networks
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Performance evaluation of basic linear algebra subroutines on a matrix co-processor
PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
A clustering model for multicast on hypercube network
GPC'08 Proceedings of the 3rd international conference on Advances in grid and pervasive computing
Communication-prediction of scouting switching in adaptively-routed torus networks
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Framework for massively parallel testing at wafer and package test
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Interconnection alternatives for hierarchical monitoring communication in parallel SoCs
Microprocessors & Microsystems
Proceedings of the twenty-second annual ACM symposium on Parallelism in algorithms and architectures
Design of a router for network-on-chip
International Journal of High Performance Systems Architecture
International Journal of High Performance Systems Architecture
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Performance modelling and analysis of interconnection networks with spatio-temporal bursty traffic
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
EDXY - A low cost congestion-aware routing algorithm for network-on-chips
Journal of Systems Architecture: the EUROMICRO Journal
Aérgia: exploiting packet latency slack in on-chip networks
Proceedings of the 37th annual international symposium on Computer architecture
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
Proceedings of the 37th annual international symposium on Computer architecture
Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluating Bufferless Flow Control for On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Design of a High-Throughput Distributed Shared-Buffer NoC Router
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Fault-Tolerant Flow Control in On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Design of High-Radix Clos Network-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Virtual point-to-point connections for NoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Improving the scalability of data center networks with traffic-aware virtual machine placement
INFOCOM'10 Proceedings of the 29th conference on Information communications
A multilayer nanophotonic interconnection network for on-chip many-core communications
Proceedings of the 47th Design Automation Conference
Virtual channels vs. multiple physical networks: a comparative analysis
Proceedings of the 47th Design Automation Conference
An efficient dynamically reconfigurable on-chip network architecture
Proceedings of the 47th Design Automation Conference
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
Journal of Parallel and Distributed Computing
Token tenure and PATCH: A predictive/adaptive token-counting hybrid
ACM Transactions on Architecture and Code Optimization (TACO)
Wavelength assignment for all-to-all broadcast in WDM optical linear array with limited drops
Computer Communications
Applying Amdahl's other law to the data center
IBM Journal of Research and Development
Microprocessors & Microsystems
On-chip network design considerations for compute accelerators
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Next generation on-chip networks: what kind of congestion control do we need?
Hotnets-IX Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks
Accelerating lightpath setup via broadcasting in binary-tree waveguide in optical NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
A method to remove deadlocks in networks-on-chips with wormhole flow control
Proceedings of the Conference on Design, Automation and Test in Europe
An analytical method for evaluating network-on-chip performance
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient lookahead routing and header compression for multicasting in networks-on-chip
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
DOS: a scalable optical switch for datacenters
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Light NUCA: a proposal for bridging the inter-cache latency gap
Proceedings of the Conference on Design, Automation and Test in Europe
A hybrid packet-circuit switched on-chip network based on SDM
Proceedings of the Conference on Design, Automation and Test in Europe
aEqualized: a novel routing algorithm for the Spidergon network on chip
Proceedings of the Conference on Design, Automation and Test in Europe
Latency criticality aware on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
An SDRAM-aware router for networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Exploring programming model-driven QoS support for NoC-based platforms
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A holistic approach to network-on-chip synthesis
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ERA: an efficient routing algorithm for power, throughput and latency in network-on-chips
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Weighted random oblivious routing on torus networks
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A novel 3D layer-multiplexed on-chip network
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
On-Chip Network Evaluation Framework
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
A first approach to king topologies for on-chip networks
Euro-Par'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part II
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Embedded network protocols for mobile devices
FMICS'10 Proceedings of the 15th international conference on Formal methods for industrial critical systems
VL2: a scalable and flexible data center network
Communications of the ACM
The general matrix multiply-add operation on 2D torus
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Software-based fault-tolerant routing algorithm in multi- dimensional networks
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Optimizing power and performance for reliable on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Efficient throughput-guarantees for latency-sensitive networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Journal of Systems Architecture: the EUROMICRO Journal
Modeling and evaluation of ring-based interconnects for Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Enabling dynamic and programmable QoS in SoCs
Proceedings of the Third International Workshop on Network on Chip Architectures
A framework for designing congestion-aware deterministic routing
Proceedings of the Third International Workshop on Network on Chip Architectures
A variable-pipeline on-chip router optimized to traffic pattern
Proceedings of the Third International Workshop on Network on Chip Architectures
An analytical approach for network-on-chip performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Throughput-Effective On-Chip Networks for Manycore Accelerators
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Adaptive Flow Control for Robust Performance and Energy
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Fast and efficient processor allocation algorithm for torus-based chip multiprocessors
Computers and Electrical Engineering
RouteBricks: enabling general purpose network infrastructure
ACM SIGOPS Operating Systems Review
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip
Microprocessors & Microsystems
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study
Microprocessors & Microsystems
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture
Microprocessors & Microsystems
Control for power gating of wires
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verifying deadlock-freedom of communication fabrics
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Power-efficient tree-based multicast support for networks-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
The Journal of Supercomputing
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
A workload-adaptive and reconfigurable bus architecture for multicore processors
International Journal of Reconfigurable Computing
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
An improvement of router throughput for on-chip networks using on-the-fly virtual channel allocation
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Energy-optimized on-chip networks using reconfigurable shortcut paths
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors
ACM Journal on Emerging Technologies in Computing Systems (JETC)
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Computer Networks: The International Journal of Computer and Telecommunications Networking
A composite and scalable cache coherence protocol for large scale CMPs
Proceedings of the international conference on Supercomputing
Formal verification of arbiters using property strengthening and underapproximations
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
HOPE: hotspot congestion control for Clos network on chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Deadlock-free fine-grained thread migration
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Prevention flow-control for low latency torus Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A vertical bubble flow network using inductive-coupling for 3-D CMPs
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
BLOCON: a bufferless photonic Clos Network-on-Chip architecture
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
DART: a programmable architecture for NoC simulation on FPGAs
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Inferring packet dependencies to improve trace based simulation of on-chip networks
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
An abacus turn model for time/space-efficient reconfigurable routing
Proceedings of the 38th annual international symposium on Computer architecture
A case for heterogeneous on-chip interconnects for CMPs
Proceedings of the 38th annual international symposium on Computer architecture
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Proceedings of the 38th annual international symposium on Computer architecture
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
Proceedings of the 38th annual international symposium on Computer architecture
Proceedings of the 38th annual international symposium on Computer architecture
PERCS: the IBM power7-IH high-performance computing system
IBM Journal of Research and Development
USENIXATC'11 Proceedings of the 2011 USENIX conference on USENIX annual technical conference
Non-existence of bipartite graphs of diameter at least 4 and defect 2
Journal of Algebraic Combinatorics: An International Journal
Proceedings of the 8th ACM International Conference on Computing Frontiers
Performance evaluation of a wormhole-routed algorithm for irregular mesh NoC interconnect
ICDCN'10 Proceedings of the 11th international conference on Distributed computing and networking
Communication performance of a recirculative omega high-speed system area network for HPC
Proceedings of the 12th International Conference on Computer Systems and Technologies
FlexiBuffer: reducing leakage power in on-chip network routers
Proceedings of the 48th Design Automation Conference
Capacity optimized NoC for multi-mode SoC
Proceedings of the 48th Design Automation Conference
OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees
Journal of Parallel and Distributed Computing
2-Dilated flattened butterfly: A nonblocking switching topology for high-radix networks
Computer Communications
Adaptive routing strategies for large scale spiking neural network hardware implementations
ICANN'11 Proceedings of the 21th international conference on Artificial neural networks - Volume Part I
Real-time communication analysis for networks with two-stage arbitration
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
Exploiting temporal decoupling to accelerate trace-driven NoC emulation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Journal of Systems and Software
Virtual path implementation of multi-stream routing in network on chip
PaCT'11 Proceedings of the 11th international conference on Parallel computing technologies
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation
ACM Transactions on Embedded Computing Systems (TECS)
Self-organizing systems based on morphogenesis principles
IBM Journal of Research and Development
Energy characteristic of a processor allocator and a network-on-chip
International Journal of Applied Mathematics and Computer Science - SPECIAL SECTION: Efficient Resource Management for Grid-Enabled Applications
3D NOC for many-core processors
Microelectronics Journal
Computers and Electrical Engineering
Computers and Electrical Engineering
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip
Proceedings of the 4th International Workshop on Network on Chip Architectures
A low-latency modular switch for CMP systems
Microprocessors & Microsystems
Stochastic communication for application-specific Networks-on-Chip
The Journal of Supercomputing
The Journal of Supercomputing
The Journal of Supercomputing
Entropy throttling: a physical approach for maximizing packet mobility in interconnection networks
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Clustering multicast on hypercube network
HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
Ethernet as a lossless deadlock free system area network
ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications
Evaluation of interconnection network performance under heavy non-uniform loads
ICA3PP'05 Proceedings of the 6th international conference on Algorithms and Architectures for Parallel Processing
SONA: an on-chip network for scalable interconnection of AMBA-Based IPs
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
Buffered deflection routing for networks-on-chip
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Designing scalable WDM optical interconnects using predefined wavelength conversion
NETWORKING'06 Proceedings of the 5th international IFIP-TC6 conference on Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communications Systems
A performance model of fault-tolerant routing algorithm in interconnect networks
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
RTTM: a new hierarchical interconnection network for massively parallel computing
HPCA'09 Proceedings of the Second international conference on High Performance Computing and Applications
X-torus: a variation of torus topology with lower diameter and larger bisection width
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part V
Application-aware deadlock-free oblivious routing based on extended turn-model
Proceedings of the International Conference on Computer-Aided Design
A low-swing crossbar and link generator for low-power networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
Proceedings of the International Conference on Computer-Aided Design
Cost / performance trade-offs and fairness evaluation of queue mapping policies
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Network-on-Chip routing algorithms by breaking cycles
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Saturating the transceiver bandwidth: switch fabric design on FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Making-a-stop: A new bufferless routing algorithm for on-chip network
Journal of Parallel and Distributed Computing
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Packet chaining: efficient single-cycle allocation for on-chip networks
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
FeatherWeight: low-cost optical arbitration with QoS support
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
TransCom: transforming stream communication for load balance and efficiency in networks-on-chip
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Formally enhanced runtime verification to ensure NoC functional correctness
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip
Computers and Electrical Engineering
Building a terabit router with XD networks
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
HotCloud'11 Proceedings of the 3rd USENIX conference on Hot topics in cloud computing
Communication based proactive link power management
Transactions on High-Performance Embedded Architectures and Compilers IV
A modular simulator framework for network-on-chip based manycore chips using UNISIM
Transactions on High-Performance Embedded Architectures and Compilers IV
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Enforcing dimension-order routing in on-chip torus networks without virtual channels
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
A simple and efficient input selection function for networks-on-chip
ICDCN'12 Proceedings of the 13th international conference on Distributed Computing and Networking
A guided tour of data-center networking
Communications of the ACM
Topology-Aware quality-of-service support in highly integrated chip multiprocessors
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Static task mapping for tiled chip multiprocessors with multiple voltage islands
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Streamlined network-on-chip for multicore embedded architectures
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
DPillar: Dual-port server interconnection network for large scale data centers
Computer Networks: The International Journal of Computer and Telecommunications Networking
Formal Methods in System Design
A high-performance online assay interpreter for digital microfluidic biochips
Proceedings of the great lakes symposium on VLSI
Benefits of selective packet discard in networks-on-chip
ACM Transactions on Architecture and Code Optimization (TACO)
A novel 3D NoC architecture based on De Bruijn graph
Computers and Electrical Engineering
A Guided Tour through Data-center Networking
Queue - Networks
Targeted random test generation for power-aware multicore designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Integration, the VLSI Journal
Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture
Proceedings of the 9th conference on Computing Frontiers
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Status data and communication aspects in dynamically clustered network-on-chip monitoring
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Intelligent on/off dynamic link management for on-chip networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Explicit modeling of control and data for improved NoC router estimation
Proceedings of the 49th Annual Design Automation Conference
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
Proceedings of the 49th Annual Design Automation Conference
Real-time network-on-chip simulation modeling
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
Optical Switching and Networking
Optical Switching and Networking
Topology Agnostic Dynamic Quick Reconfiguration for Large-Scale Interconnection Networks
CCGRID '12 Proceedings of the 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012)
High-throughput differentiated service provision router architecture for wireless network-on-chip
International Journal of High Performance Systems Architecture
A micro-architectural analysis of switched photonic multi-chip interconnects
Proceedings of the 39th Annual International Symposium on Computer Architecture
A case for random shortcut topologies for HPC interconnects
Proceedings of the 39th Annual International Symposium on Computer Architecture
Theoretical Computer Science
Bisection (band)width of product networks with application to data centers
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
NetPilot: automating datacenter network failure mitigation
Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
Caesar: a content router for high speed forwarding
Proceedings of the second edition of the ICN workshop on Information-centric networking
Optimizing heterogeneous NoC design
Proceedings of the International Workshop on System Level Interconnect Prediction
Flexible router architecture for network-on-chip
Computers & Mathematics with Applications
Design and implementation of multi-camera systems distributed over a spherical geometry
Diagrams'12 Proceedings of the 7th international conference on Diagrammatic Representation and Inference
Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks
Journal of Parallel and Distributed Computing
Efficient implementation of globally-aware network flow control
Journal of Parallel and Distributed Computing
An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip
Microprocessors & Microsystems
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms
Microprocessors & Microsystems
APCR: an adaptive physical channel regulator for on-chip interconnects
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
NetPilot: automating datacenter network failure mitigation
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A framework for low-communication 1-D FFT
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Concerning with on-chip network features to improve cache coherence protocols for CMPs
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Performance and complexity analysis of credit-based end-to-end flow control in network-on-chip
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
Stochastic communication delay analysis of adaptive wormhole-switched routings in tori with faults
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
RDMA in the SiCortex cluster systems
PVM/MPI'07 Proceedings of the 14th European conference on Recent Advances in Parallel Virtual Machine and Message Passing Interface
A new load balanced routing algorithm for torus networks
ESCAPE'07 Proceedings of the First international conference on Combinatorics, Algorithms, Probabilistic and Experimental Methodologies
Surface wave communication system for on-chip and off-chip interconnects
Proceedings of the Fifth International Workshop on Network on Chip Architectures
Junction based routing: a scalable technique to support source routing in large NoC platforms
Proceedings of the Fifth International Workshop on Network on Chip Architectures
Proceedings of the Fifth International Workshop on Network on Chip Architectures
Low power flitwise routing in an unidirectional torus with minimal buffering
Proceedings of the Fifth International Workshop on Network on Chip Architectures
Towards an efficient fat-tree like topology
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
PAST: scalable ethernet for data centers
Proceedings of the 8th international conference on Emerging networking experiments and technologies
Functional post-silicon diagnosis and debug for networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
TRACKER: a low overhead adaptive NoC router with load balancing selection strategy
Proceedings of the International Conference on Computer-Aided Design
Synthesis and optimization of reversible circuits—a survey
ACM Computing Surveys (CSUR)
Network-on-chip traffic modeling for data flow applications
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
An energy- and buffer-aware fully adaptive routing algorithm for Network-on-Chip
Microelectronics Journal
Moths: Mobile threads for on-chip networks
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Heracles: a tool for fast RTL-based design space exploration of multicore processors
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A latency-optimized hybrid network for clustering FPGAs (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
International Journal of Embedded and Real-Time Communication Systems
Scalable load balancing congestion-aware Network-on-Chip router architecture
Journal of Computer and System Sciences
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Addressing End-to-End Memory Access Latency in NoC-Based Multicores
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 27th international ACM conference on International conference on supercomputing
Randomizing task placement does not randomize traffic (enough)
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip
SMART: a single-cycle reconfigurable NoC for SoC applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
DeBAR: deflection based adaptive router with minimal buffering
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Catnap: energy proportional multiple network-on-chip
Proceedings of the 40th Annual International Symposium on Computer Architecture
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip
Proceedings of the 40th Annual International Symposium on Computer Architecture
Gana: A novel low-cost conflict-free NoC architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Proceedings of the ACM SIGCOMM 2013 conference on SIGCOMM
Designing energy-efficient NoC for real-time embedded systems through slack optimization
Proceedings of the 50th Annual Design Automation Conference
21st century digital design tools
Proceedings of the 50th Annual Design Automation Conference
Randomized partially-minimal routing: near-optimal oblivious routing for 3-D mesh networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and implementation of an on-chip permutation network for multiprocessor system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An MILP-based aging-aware routing algorithm for NoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Scalable progress verification in credit-based flow-control systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Congestion-aware scheduling for NoC-based reconfigurable systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
High and stable performance under adverse traffic patterns of tori-connected torus network
Computers and Electrical Engineering
A new routing scheme for Jellyfish and its performance with HPC workloads
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
An energy-aware online task mapping algorithm in NoC-based system
The Journal of Supercomputing
Multiswapped networks and their topological and algorithmic properties
Journal of Computer and System Sciences
A unified link-layer fault-tolerant architecture for network-based many-core embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs
Journal of Systems Architecture: the EUROMICRO Journal
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
Designing on-chip networks for throughput accelerators
ACM Transactions on Architecture and Code Optimization (TACO)
Scalable high-radix router microarchitecture using a network switch organization
ACM Transactions on Architecture and Code Optimization (TACO)
L24: Parallelism, performance, energy efficiency, and cost trade-offs in future sensor platforms
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Electrical and Computer Engineering
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
On-chip ring network designs for hard-real time systems
Proceedings of the 21st International conference on Real-Time Networks and Systems
Memory-centric system interconnect design with hybrid memory cubes
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
McRouter: multicast within a router for high performance network-on-chips
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
Making the network scalable: inter-subnet routing in infiniband
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Network-aware virtual machine consolidation for large data centers
NDM '13 Proceedings of the Third International Workshop on Network-Aware Data Management
On multicast for dynamic and irregular on-chip networks using dynamic programming method
Proceedings of the Sixth International Workshop on Network on Chip Architectures
LEF: long edge first routing for two-dimensional mesh network on chip
Proceedings of the Sixth International Workshop on Network on Chip Architectures
An analytical model for on-chip interconnects in multimedia embedded systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture
Journal of Parallel and Distributed Computing
Optimal networks from error correcting codes
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus
Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Performance implications of remote-only load balancing under adversarial traffic in Dragonflies
Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Journal of Systems Architecture: the EUROMICRO Journal
VBON: Toward efficient on-chip networks via hierarchical virtual bus
Microprocessors & Microsystems
Dual partitioning multicasting for high-performance on-chip networks
Journal of Parallel and Distributed Computing
Direct distributed memory access for CMPs
Journal of Parallel and Distributed Computing
PAIS: Parallelism-aware interconnect scheduling in multicores
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
On the topological properties of HyperX
The Journal of Supercomputing
TM: a new and simple topology for interconnection networks
The Journal of Supercomputing
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
A framework for low-communication 1-D FFT
Scientific Programming - Selected Papers from Super Computing 2012
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