Measuring jitter of high speed data channels using undersampling techniques
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
High speed serial transceivers for data communication systems
IEEE Communications Magazine
| Hi-index | 0.00 |
High-speed communications link cores must consume low-power, feature low bit-error-rates (BER), and address many applications. We present a methodology to design adaptive link architectures, whereby the link's internal logic complexity, frequency, and supply are simultaneously adapted to application requirements. The requirement space is mapped to the design space using requirements measurement circuits and configurable logic blocks. CMOS results indicate that power savings of 60 versus the worst case are possible, while the area overhead is kept under 5.