Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining

Authors:
Lizheng Zhang;Yuhen Hu;Charlie, Chungping Chen
Affiliations:
University of Wisconsin, Madison, WI;University of Wisconsin, Madison, WI;National Taiwan University, Taipei, Taiwan
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

Citing 16
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Abstract

With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, a novel statistical timing analysis approach has been developed to analyze the behavior of two important pipelined architectures for multiple clock-cycle global interconnect, namely, the flip-flop inserted global wire and the latch inserted global wire. We present analytical formula that is based on parameters obtained using Monte Carlo simulation. These results enable a global interconnect designer to explore design trade-offs between clock frequency and probability of bit-error during data transmission.