Property Checking based on Hierarchical Integer Equations

• Venue: ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
• Year: 2004

This article describes a high level model of digitalcircuits for application of formal verification propertiesat this level. In our method, a behavioral state machine isrepresented by a multiplexer based structure of linearinteger equations, and RT level properties are directlyapplied. It reduces the need for large BDD datastructures and uses far less memory. Furthermore, thereis no need to separate the data and control sections incircuits. We used a canonical form of linear TED [Taylor Expansion Diagrams: A Compact Canonical Representation for Arithmetic Expressions].This paper compares our results with those of the VISverification tool which is a BDD based program. Also wewill run it on gate level designs.