"AU: Timing Analysis Under Uncertainty

Authors:
Sarvesh Bhardwaj;Sarma B. K. Vrudhula;David Blaauw
Affiliations:
University of Arizona;University of Arizona;University of Michigan
Venue:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Year:
2003

Citing 9
Cited 24

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Abstract

Due to excessive reduction in the gate length, dopant concentrationsand the oxide thickness, even the slightest of variations inthese quantities can result in significant variations in the performanceof a device. This has resulted in a need for efficient andaccurate techniques for performing Statistical Analysis of circuits.In this paper we propose a methodology based on Bayesian Networksfor computing the exact probability distribution of the delayof a circuit. In case of large circuits where it is not possible tocompute the exact distribution, we propose methods to reduce theproblem size and get a tight lower bound on the exact distribution.