Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Subwavelength optical lithography: challenges and impact on physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Proceedings of the 37th Annual Design Automation Conference
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Explicit computation of performance as a function of process variation
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis of Combinational Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
A New Statistical Approach to Timing Analysis of VLSI Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Reducing pipeline energy demands with local DVS and dynamic retiming
Proceedings of the 2004 international symposium on Low power electronics and design
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On Statistical Timing Analysis with Inter- and Intra-Die Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Optimization objectives and models of variation for statistical gate sizing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
CAD tools for variation tolerance
Proceedings of the 42nd annual Design Automation Conference
Efficient statistical timing analysis through error budgeting
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Clock schedule verification under process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Block based statistical timing analysis with extended canonical timing model
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Hierarchical analysis of process variation for mixed-signal systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
Timing analysis in presence of supply voltage and temperature variations
Proceedings of the 2006 international symposium on Physical design
Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis
Proceedings of the 2006 international symposium on Physical design
Fast buffer insertion considering process variations
Proceedings of the 2006 international symposium on Physical design
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Advances in Computation of the Maximum of a Set of Random Variables
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Delay Fault Diagnosis for Non-Robust Test
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Bringing Manufacturing into Design via Process-Dependent SPICE Models
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Application of fast SOCP based statistical sizing in the microprocessor design flow
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Synthesis methodology for built-in at-speed testing
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis with two-sided constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical timing analysis with path reconvergence and spatial correlations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Refined statistical static timing analysis through
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing On-Die Process Variation in Nanometer VLSI
IEEE Design & Test
Yield-Aware Cache Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Temperature and voltage aware timing analysis: application to voltage drops
Proceedings of the conference on Design, automation and test in Europe
A novel criticality computation method in statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Fast second-order statistical static timing analysis using parameter dimension reduction
Proceedings of the 44th annual Design Automation Conference
Design-silicon timing correlation: a data mining perspective
Proceedings of the 44th annual Design Automation Conference
Extraction of statistical timing profiles using test data
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The effect of process variation on device temperature in FinFET circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design Considerations for High Performance RF Cores Based on Process Variation Study
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Static timing: back to our roots
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Within-die process variations: how accurately can they be statistically modeled?
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
VariaSim: simulating circuits and systems in the presence of process variability
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
A lithography-friendly structured ASIC design approach
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
An expected-utility based approach to variation aware VLSI optimization under scarce information
Proceedings of the 13th international symposium on Low power electronics and design
Variation-aware gate sizing and clustering for post-silicon optimized circuits
Proceedings of the 13th international symposium on Low power electronics and design
Proceedings of the conference on Design, automation and test in Europe
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
Latch modeling for statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Measuring and modeling variabilityusing low-cost FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Efficient block-based parameterized timing analysis covering all potentially critical paths
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Process variability-aware transient fault modeling and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A statistical approach for full-chip gate-oxide reliability analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Accelerating statistical static timing analysis using graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Shapeshifter: Dynamically changing pipeline width and speed to address process variations
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Statistical static timing analysis: A survey
Integration, the VLSI Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
Timing-aware multiple-delay-fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process variation-aware performance analysis of asynchronous circuits
Microelectronics Journal
Design and test strategies for microarchitectural post-fabrication tuning
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Process-induced skew variation for scaled 2-D and 3-D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
Proceedings of the 47th Design Automation Conference
MODEST: a model for energy estimation under spatio-temporal variability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Non-linear operating point statistical analysis for local variations in logic timing at low voltage
Proceedings of the Conference on Design, Automation and Test in Europe
Digital design at a crossroads: how to make statistical design methodologies industrially relevant
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical approach in a system level methodology to deal with process variation
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-level reliability modeling for MPSoCs
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical leakage power optimization of asynchronous circuits considering process variations
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Estimation of FMAX and ISB in microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical timing yield optimization by gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ordered coloring-based resource binding for datapaths with improved skew-adjustability
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Handling intra-die variations in PSTA
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
Fast estimation of timing yield bounds for process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Data memory subsystem resilient to process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Proceedings of the 48th Design Automation Conference
Computers and Electrical Engineering
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Delay-correlation-aware SSTA based on conditional moments
Microelectronics Journal
Statistical characterization of library timing performance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Reversible statistical max/min operation: concept and applications to timing
Proceedings of the 49th Annual Design Automation Conference
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Computation of joint timing yield of sequential networks considering process variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Asymmetric-access aware optimization for STT-RAM caches with process variations
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Statistical modeling with the virtual source MOSFET model
Proceedings of the Conference on Design, Automation and Test in Europe
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
Proceedings of the 40th Annual International Symposium on Computer Architecture
Hardware/software approaches for reducing the process variation impact on instruction fetches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
3DHLS: incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and design exploration of FBDRAM as on-chip memory
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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Process variations have become a critical issue in performanceverification of high-performance designs. We present a new, statisticaltiming analysis method that accounts for inter- and intra-dieprocess variations and their spatial correlations. Since statisticaltiming analysis has an exponential run time complexity, we proposea method whereby a statistical bound on the probability distributionfunction of the exact circuit delay is computed with linear run time.First, we develop a model for representing inter- and intra-die variationsand their spatial correlations. Using this model, we thenshow how gate delays and arrival times can be represented as a sumof components, such that the correlation information betweenarrival times and gate delays is preserved. We then show howarrival times are propagated and merged in the circuit to obtain anarrival time distribution that is an upper bound on the distributionof the exact circuit delay. We prove the correctness of the bound andalso show how the bound can be improved by propagating multiplearrival times. The proposed algorithms were implemented andtested on a set of benchmark circuits under several process variationscenarios. The results were compared with Monte Carlo simulationand show an accuracy of 3.32% on average over all test cases.