Automatic Generation of Virtual Prototypes

Authors:
P. Belanovic;M. Holzer;B. Knerr;M. Rupp;G. Sauzon
Affiliations:
Vienna University of Technology;Vienna University of Technology;Vienna University of Technology;Vienna University of Technology;Infineon Technologies
Venue:
RSP '04 Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping
Year:
2004

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A fully automated environment for verification of virtual prototypes

EURASIP Journal on Applied Signal Processing

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Abstract

Virtual prototyping as an embedded system design techniquehas the potential to significantly increase efficiency ofthe design process. An environment for automatic generationof virtual prototypes (VPs) directly from algorithmic-leveldescriptions is presented here. It is implemented aspart of a unified design methodology and produces VSIAcompliant VPs. When applied to an industrial design flowof a UMTS receiver, this environment for automatic generationof VPs produced significant speedups over traditionalmanual VP creation, with savings in the order of hundredsto thousands of person-hours.