Design and Application of Amplitude-Locked Loop Separation System Based on SignalWAVe
Wireless Personal Communications: An International Journal
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FPGA Co-simulation of an IP core is animportant design flow step in IP and SystemDevelopment. In this paper we discuss how, withXilinxýs System Generator for DSP 3.1 (XSG), it ispossible for multiple-users to hardware cosimulateIP cores over any distance via TCP/IP,sharing only one FPGA board resource. Thehardware co-simulation strategy is mutuallyexclusive in that only one user at any one timecan hardware co-simulate on the FPGA board.We demonstrate this with the use of twoencryption cores, Camellia and AES-128(Advanced Encryption Standard), which haveboth been generated using the block-based tool.The sharing of the FPGA board is handled with aset of Matlab function commands.