Parallel parsing in a multiprocessor environment
Parallel parsing in a multiprocessor environment
Upper Bounds for Speedup in Parallel Parsing
Journal of the ACM (JACM)
A Survey of Parallel Machine Organization and Programming
ACM Computing Surveys (CSUR)
Parallel Generation of Postfix and Tree Forms
ACM Transactions on Programming Languages and Systems (TOPLAS)
Analyses of deterministic parsing algorithms
Communications of the ACM
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
The Theory of Parsing, Translation, and Compiling
The Theory of Parsing, Translation, and Compiling
Parallel Compilation In A Multiprocessor Environment (Extended Abstract)
ACM '78 Proceedings of the 1978 annual conference
Lexical analysis and parsing techniques for a vector machine
Proceedings of the conference on Programming languages and compilers for parallel and vector machines
A parallel approach to code generation for Fortran like compilers
Proceedings of the conference on Programming languages and compilers for parallel and vector machines
ACM '71 Proceedings of the 1971 26th annual conference
On parsing context free languages in parallel environments.
On parsing context free languages in parallel environments.
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Scanning regular languages by dual finite automata
ACM SIGPLAN Notices
Parallel parsing of operator precedence grammars
Information Processing Letters
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A method for estimating the speedup for asynchronous bottom-up parallel parsing is presented. Two models for bottom-up parallel parsing are proposed, and the speedup for each of the two models is estimated. The speedup obtained for model A is a very close to the simulation result already available in literature; however, the model is restrictive because it can only communicate with its immediate left and right neighbors. This increases the processor coordination and interprocessor communication times. Model B, while showing a greater speedup time, is expensive to construct when the number of processors is large.