A sub-mW MPEG-4 motion estimation processor core for mobile video application

Authors:
Y. Kuroda;J. Miyakoshi;M. Miyama;K. Imamura;H. Hashimoto;M. Yoshimoto
Affiliations:
Kanazawa University, Kodatsuno, Kanazawa, Japan;Kanazawa University, Kodatsuno, Kanazawa, Japan;Kanazawa University, Kodatsuno, Kanazawa, Japan;Kanazawa University, Kodatsuno, Kanazawa, Japan;Kanazawa University, Kodatsuno, Kanazawa, Japan;Kanazawa University, Kodatsuno, Kanazawa, Japan
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

Citing 1
Cited 1

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

Low-Power MPEG-4 motion estimator design for deep sub-micron multimedia soc

KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part III

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Abstract

This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a Gradient Descent Search algorithm whose computation power is only 7% of the conventional 1:4-subsampling search, producing higher picture quality. Another feature is an optimized SIMD datapath architecture to decrease a clock frequency and an operating voltage. It has been fabricated with CMOS 5-metal 0.18 um technology. The measured power consumption to process a QCIF 15 fps video is 0.4 mW under 0.85 MHz@1.0 V.