350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node

Authors:
Takashi Morimoto;Yohmei Harada;Tetsushi Koide;Hans Jürgen Mattausch
Affiliations:
Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan;Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan;Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan;Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

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Abstract

We designed a cell-network-based full-custom test-chip for gray-scale/color image segmentation of real-time video-signals in 350nm CMOS technology. From this digital test-chip design, fully-integrated QVGA-size video-picture-segmentation chips, with 250μsec segmentation time per frame, at 10MHz are estimated to become possible at the 90nm technology node.