The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
Communications of the ACM
RESST: A VLSI Implementation of a Record-Sorting Stack
RESST: A VLSI Implementation of a Record-Sorting Stack
A Special-Function Unit for Sorting and Sort-Based Database Operations
IEEE Transactions on Computers
A Fault-Tolerant Systolic Sorter
IEEE Transactions on Computers
A Special Function Unit for Database Operations (SFU-DB): Design and Performance Evaluation
IEEE Transactions on Computers
A novel overlap-based logic cell: an efficient implementation of flip-flops with embedded logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A hardware sort-merge system which can sort large files rapidly is proposed. It consists of an initial sorter and a pipelined merger. In the initial sorter, record sorting is divided into two parts: key-pointer sorting and record rearranging. The pipelined merger is composed of several intelligent disks each of which has a simple processor and some buffers. The hardware sort-merge system can sort files of any size by using the pipelined merger repeatedly. The key-pointer sorting circuit in the initial sorter requires only unidirectional connections between neighboring cells, instead of the usual bidirectional ones. The initial sorter can also generate sorted sequences longer than its capacity so that the number of merging passes can be reduced. A new data management scheme is proposed to run all merging passes in a pipelined fashion.