Novel method for analysis of printed circuit images

  • Authors:
  • Jon R. Mandeville

  • Affiliations:
  • IBM Research Divsion, P. O. Box 218, Yorktown Heights, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 1985

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Abstract

To keep pace with the trend towards increased circuit integration, printed circuit patterns are becoming denser and more complex. A variety of automated visual inspection methods to detect circuit defects during manufacturing have been proposed. This paper describes a method which is a synthesis of the reference-comparison and the generic-property approaches that exploits their respective strengths and overcomes their respective weaknesses. It is based on the observation that the local geometric and global topological correctness of a printed circuit can be inferred from the correctness of simplified, skeletal versions of the circuit in a test image. These operations can be realized using simple processing elements which are well suited for implementation in hardware.