Journal of Electronic Testing: Theory and Applications
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Critical dimensions are scaling faster than our control of them. In addition to manufacturing variations, chip design has to deal with wear-out phenomena and dynamic changes in temperature or power-supply voltage. As a result, parametric delay variability is proportionately increasing with each new generation of technology, as is leakage power variability. Further, the number of independent and significant sources of variability is rapidly increasing. These effects present two key challenges: timing verification and robust design in the presence of uncertainties. This presentation will describe the role of statistical timing in addressing these challenges and the concomitant shift in chip design methodology from a deterministic to a probabilistic paradigm. The importance of correctly capturing correlations will be stressed. Different methods of statistical timing and their relative merits will be discussed. The diagnostics provided by statistical timers and the use of such diagnostics in targeting robust design will be presented.