S/390 parallel enterprise server generation 3: a balanced system and cache structure
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Run-control and service element code simulation for the S/390 microprocessor
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
z990 netmessage-protocol-based processor to support element communication interface
IBM Journal of Research and Development
RAS strategy for IBM S/390 G5 and G6
IBM Journal of Research and Development
System control structure of the IBM eServer z900
IBM Journal of Research and Development
z990 netmessage-protocol-based processor to support element communication interface
IBM Journal of Research and Development
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This paper describes the migration of the hardware-implemented run-control functions from a single-book structure with one flexible service processor (FSP) and one service element (SE) per system to a multibook structure with one FSP per book and one SE per system. The new system structure required two new interfaces between the clock chips on the different books. The first interface is required for dynamic configuration data exchange between books. The alternative path via the SE would not meet the performance requirements. This interface is available in the initial millicode load flow before the L2 caches with their ring structure are operational. Another requirement is the necessity of starting and stopping all books synchronously. The second additional interface between the clock chips on different books enables this function. Nevertheless, the hardware implementation is so flexible that each book may operate independently of the other books. The clock chips are connected as a peer-to-peer network, so no special master is necessary in the system.