Logic testing and design for testability
Logic testing and design for testability
Numerical recipes: the art of scientific computing
Numerical recipes: the art of scientific computing
Group Properties of Cellular Automata and VLSI Applications
IEEE Transactions on Computers
Random sequence generation by cellular automata
Advances in Applied Mathematics
Signature Analysis for Multiple-Output Circuits
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Cellular Automata-Based Signature Analysis for Built-In Self-Test
IEEE Transactions on Computers
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Simulation Modeling and Analysis
Simulation Modeling and Analysis
Shift Register Sequences
Boundary Scan with Built-In Self-Test
IEEE Design & Test
The theory of signature testing for VLSI
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Parallel computation of non-deterministic algorithms in vlsi
Parallel computation of non-deterministic algorithms in vlsi
Error Control Coding, Second Edition
Error Control Coding, Second Edition
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Measures of the Effectiveness of Fault Signature Analysis
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
Analysis of Periodic and Intermediate Boundary 90/150 Cellular Automata
IEEE Transactions on Computers
On the Use of Counters for Reproducing Deterministic Test Sets
IEEE Transactions on Computers
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator
IEEE Transactions on Computers
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Design of CAECC - Cellular Automata Based Error Correcting Code
IEEE Transactions on Computers
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Deterministic Test Pattern Reproduction by a Counter
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Cellular Automata for Generating Deterministic Test Sequences
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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