Reverberation canceling wireless aid for hearing impaired
Analog Integrated Circuits and Signal Processing
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This paper examines the design and implementation of a single-loop second-order CMOS sigma-delta Modulator for digital audio hearing-aid applications.The Modulator circuit features reduced complexity, area reduction and low conversion energy.It has a sampling rate of 8.2MHz with an over-sampling ratio (OSR) of 256 to provide an audio bandwidth of 16kHz.The modulator is implemented in a 0.18驴m CMOS technology with metal-to-metal sandwich structure capacitors.It operates with a supply voltage of 1.8V.The active area is 0.403 mm^2.The modulator achieves a 98dB signal-to-noise-and-distortion ratio (SNDR) and a 100dB dynamic range (DR) at a Nyquist conversion rate of 32kHz and consumes 1321驴W with a joule/conversion figure of merit equal to 161x10{-12} J/s.