Interconnect Synthesis for Systems on Chip

Authors:
Neal K. Bambha;Shuvra S. Bhattacharyya
Affiliations:
University of Maryland;University of Maryland
Venue:
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Year:
2004

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A domain specific interconnect for reconfigurable computing

Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems

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Abstract

We describe an algorithm for performing a joint scheduling/interconnectsynthesis optimization for System-on-Chip (SoC) architectures. The algorithm is able to account for different distributions of long vs. short interconnect routes in an architecture. It is based on a genetic algorithm, and utilizes a graph isomorphism test to significantly pare the search space and increase the search efficiency.