An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures

  • Authors:

  • Tomasz Madajczak

  • Affiliations:

  • Technical University of Gdansk, Poland

  • Venue:
  • PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
  • Year:
  • 2004

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Abstract

This document presents a theoretical analysis of state-of-the-art hardware threading approaches such as Switch on Event Multi Threading (SoEMT) and Simultaneous Multi Threading (SMT). It proposes that the On-Demand Virtual Single-Instruction-Multiple-Data (ODVSIMD) abstraction model is a very efficientmethod of hardware threading in certain scenarios. The principles of ODVSIMD abstraction model are defined. Then, there is a proposition of the application for this abstraction model that is the data-driven automated loop partitioning. The document shows how the DOALL and DOACROSS loops can be parallelized with auto-partitioning to the ODVSIMD abstraction. This document then presents the results of parallel execution of both loop types. The results are obtained with a worksheet simulation. The document also discusses the main differences between SoEMT and SMT architectures in the context achievable performance.