HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder

Authors:
Matjaz Verderber;Andrej Zemva;Damjan Lampret
Affiliations:
University of Ljubljana;University of Ljubljana;Flextronics Design
Venue:
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Year:
2003

Citing 4
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Abstract

In this paper, we propose an optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made time/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for HW implementation of the IDCT and VLD algorithms. Remaining parts were realized in SW with 32-bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in Verilog/VHDL and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on the Flextronics prototyping board.