Tradeoffs between low complexity, low latency, and fairness with deficit round-robin schedulers

  • Authors:

  • Luciano Lenzini;Enzo Mingozzi;Giovanni Stea

  • Affiliations:

  • Dipartimento di Ingegneria della Informazione, University of Pisa, 56122 Pisa, Italy;Dipartimento di Ingegneria della Informazione, University of Pisa, 56122 Pisa, Italy;Dipartimento di Ingegneria della Informazione, University of Pisa, 56122 Pisa, Italy

  • Venue:
  • IEEE/ACM Transactions on Networking (TON)
  • Year:
  • 2004

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Abstract

Deficit Round-Robin (DRR) is a scheduling algorithm devised for providing fair queueing in the presence of variable length packets. The main attractive feature of DRR is its simplicity of implementation: in fact, it can exhibit O(1) complexity, provided that specific allocation constraints are met. However, according to the original DRR implementation, meeting such constraints often implies tolerating high latency and poor fairness. In this paper, we first derive new and exact bounds for DRR latency and fairness. On the basis of these results, we then propose a novel implementation technique, called Active List Queue Method (Aliquem), which allows a remarkable gain in latency and fairness to be achieved, while still preserving O(1) complexity. We show that DRR achieves better performance metrics than those of other round-robin algorithms such as Pre-Order Deficit Round-Robin and Smoothed Round-Robin. We also show by simulation that the proposed implementation allows the average delay and the jitter to be reduced.