An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2^n)

  • Authors:

  • Lo'ai A. Tawalbeh;Alexandre F. Tenca

  • Affiliations:

  • Oregon State University, USA;Oregon State University, USA

  • Venue:
  • ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
  • Year:
  • 2004

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Abstract

This paper presents an algorithm and architecture that integrates modular division and multiplication in both GF(p) and GF(2^n) fields (Unified).The algorithm is based on the Extended Binary GCD algorithm for modular division and on the Montgomery's method for modular multiplication.For the division operation, the proposed algorithm uses a counter to keep track of the difference between two field elements and this way eliminate the need for comparisons which are usually expensive and time-consuming.The proposed architecture efficiently supports all the operations in the algorithm and uses carry-save unified adders for reduced critical path delay, making the proposed architecture faster than other previously proposed designs.Experimental results using synthesis for AMI 0.5驴m CMOS technology are shown and compared with other dividers and multipliers.