Time-Critical Software Deceleration in an FCCM

Authors:
Phil James-Roxby;Gordon Brebner;Dennis Bemmann
Affiliations:
Xilinx Research Labs, Longmont, CO, USA;Xilinx Research Labs, San Jose, CA, USA;Humboldt University, Berlin, Germany
Venue:
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2004

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Abstract

In this paper, we explore two important latency issues associated with using an embedded processor as an assistant to programmable logic within a logic-centric system implemented ona platform FPGA. The context is that of the 'software decelerator' - a term introduced by the authors in 2003 to describe a logic-centric counterpart of the familiar hardware accelerator.We first focus on minimizing latency in the logic-processor interface, introducing an efficient interrupt-driven control mechanism. Then, in the context of a case study on packet address lookup, we focus on minimizing latency in memory interfaces, using the processor's hardware cache mechanism for assistance.