FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm

Authors:
Deepak Boppana;Kully Dhanoa;Jesse Kempa
Affiliations:
Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA
Venue:
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2004

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Abstract

A novel implementation of the QR decomposition based recursive least squares (RLS) algorithm on Altera Stratix FPGAs is presented. CORDIC (Coordinate Rotation by Digital Computer) operators are efficiently time-shared to perform the QR decomposition while consuming minimal resources. Back substitution is then performed on the embedded soft Nios processor by utilizing custom instructions to yield the final weight vectors. Analytical resource estimates along with actual implementation results illustrating the weight calculation delays are also presented.