Modeling subthreshold SOI logic for static timing analysis

Authors:
Alexandre Valentian;Olivier Thomas;Andrei Vladimirescu;Amara Amara
Affiliations:
Institute Supérieur d'Electronique de Paris (ISEP), 75006 Paris, France;ISEP, 75006 Paris, France;ISEP and the Berkeley Wireless Research Center, University of California, Berkeley, CA;ISEP, 75006 Paris, France
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

Citing 1
Cited 1

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

Analog Integrated Circuits and Signal Processing - Special issue: low-voltage low-power analog integrated circuits

Exact distribution of the max/min of two Gaussian random variables

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A simple, yet realistic physics-based model is introduced to describe the subthreshold drain current of a MOSFET taking into account the body-and drain-voltage dependencies, including the short channel effects. This model, verified by SPICE simulations, describes adequately the pseudotriode and pseudosaturation regions of MOS transistors operated below VT. It can be applied for predicting bulk-or partially depleted (PD) SOI CMOS circuit operation. Analytical expressions derived for the logic switching threshold and delay are applied to predict the performance of CMOS-SOI inverters.