The design and analysis of a quantitative simulator for dynamic memory management

  • Authors:

  • Chia-Tien Dan Lo;Witawas Srisa-an;J. Morris Chang

  • Affiliations:

  • Department of Computer Science, University of Texas at San Antonio, 6900 N, Loop 1604 W., San Antonio TX;Department of Computer Science and Engineering, University of Nebraska at Lincoln and Department of Computer Science, University of Texas at San Antonio, 6900 N, Loop 1604 W., San Antonio TX;Department of Electrical and Computer Engineering Iowa State University and Department of Computer Science, University of Texas at San Antonio, 6900 N, Loop 1604 W., San Antonio TX

  • Venue:
  • Journal of Systems and Software
  • Year:
  • 2004

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Abstract

The use of object-oriented programming in software development allows software systems to be more robust and more maintainable. At the same time, the development time and expense are also reduced. To achieve these benefits, object-oriented applications use dynamic memory management (DMM) to create generic objects that can be reused. Consequently, these applications are often highly dynamic memory intensive. For the last three decades, several DMM schemes have been proposed. Such schemes include first fit, best fit. segregated fit, and buddy systems. Because the performance (e.g., speed, memory utilization, etc.) of each scheme differs, it becomes a difficult choice in selecting the most suitable approach for an application and what parameters (e.g., block size. etc.) should be adopted. In this paper, a DMM simulation tool and its usage are presented. This tool receives DMM traces of C/C++ or Java programs and performs simulation according to the scheme (first fit, best fit, buddy system, and segregated fit) defined by the user. Techniques required to obtain memory traces are presented. At the end of each simulation run, a variety of performance metrics are reported to the users. By using this tool, software engineers can evaluate system performance and decide which algorithm is the most suitable. Moreover, hardware engineers can perform a system analysis before hardware (e.g., modified buddy system, first fit, etc.) is fabricated.