Processing issues in top-down approaches to quantum computer development in Silicon

  • Authors:

  • S.-J. Park;A. Persaud;J. A. Liddle;J. Nilsson;J. Bokor;D. H. Schneider;I. W. Rangelow;T. Schenkel

  • Affiliations:

  • Lawrence Berkeley National Laboratory, Berkeley, CA;Lawrence Berkeley National Laboratory, Berkeley, CA;Lawrence Berkeley National Laboratory, Berkeley, CA;Lawrence Livermore National Laboratory, Livermore, CA;Lawrence Berkeley National Laboratory, Berkeley, CA and Department of EECS, University of California, Berkeley, CA;Department of EECS, University of California, Berkeley, CA;Institute of Microstructure Technologies and Analytics, University of Kassel, Germany;Lawrence Berkeley National Laboratory, Berkeley, CA

  • Venue:
  • Microelectronic Engineering - Proceedings of the 29th international conference on micro and nano engineering
  • Year:
  • 2004

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Abstract

We describe critical processing issues in our development of single-atom devices for solid-state quantum information processing. Integration of single 31P atoms with control gates and single electron transistor (SET) readout structures is addressed in a silicon-based approach. Results on electrical activation of low-energy (15 keV) P implants in silicon show a strong dose effect on the electrical activation fractions. We identify dopant segregation to the SiO2/Si interface during rapid thermal annealing as a dopant loss mechanism and discuss means to minimize it. Silicon nanowire SET pairs with nanowire width of 10-20 nm are formed by electron-beam lithography in SOI. We present initial results from Coulomb blockade experiments and discuss issues of control gate integration for sub-40 nm gate pitches.