High-speed local area networks and their performance: a survey
ACM Computing Surveys (CSUR)
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
An automatic trace analysis tool generator for Estelle specifications
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Model checking for programming languages using VeriSoft
Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Bandera: extracting finite-state models from Java source code
Proceedings of the 22nd international conference on Software engineering
Verisim: Formal Analysis of Network Simulations
IEEE Transactions on Software Engineering
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
Software model checking in practice: an industrial case study
Proceedings of the 24th International Conference on Software Engineering
Automated Software Engineering
Synthesizing Monitors for Safety Properties
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Computer-assisted assume/guarantee reasoning with VeriSoft
Proceedings of the 25th International Conference on Software Engineering
Bogor: an extensible and highly-modular software model checking framework
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
Runtime safety analysis of multithreaded programs
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
An Overview of the Runtime Verification Tool Java PathExplorer
Formal Methods in System Design
Efficient Decentralized Monitoring of Safety in Distributed Systems
Proceedings of the 26th International Conference on Software Engineering
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In run-time safety analysis the executions of a concurrent program are monitored and analyzed with respect to safety properties. Similar to testing, run-time analysis is quite efficient, but it also tends to be incomplete. The results pertain only to the observed executions which may constitute just a small subset of all possible executions. In this paper, we describe a tool called ViP which uses the software model checker VeriSoft to perform comprehensive run-time safety analyses of concurrent C/C++ programs. A ViP analysis proceeds in three fully automated steps: First, the input program is prepared for a VeriSoft analysis through instrumentation. Next, VeriSoft is invoked to generate the traces corresponding to all possible executions of the program. Then, the traces are checked efficiently for specification violations. The instrumentation is based on the source code transformation language TXL. TXL allows for the instrumentation to be described in terms of rewrite rules and gives ViP a remarkable amount of flexibility. The paper describes ViP together with its use of VeriSoft and TXL. Several sample analyses are discussed to illustrate the use of ViP.