Creating a flexible, simulation-based finite scheduling tool
Proceedings of the 29th conference on Winter simulation
Efficient simulation/optimization of dispatching priority with “fake” processing time
Proceedings of the 29th conference on Winter simulation
Simulation based cause and effect analysis of cycle time distribution in semiconductor backend
Proceedings of the 32nd conference on Winter simulation
Simulation Modeling and Analysis
Simulation Modeling and Analysis
A simulation-based approach to trade-off analysis of port security
Proceedings of the 38th conference on Winter simulation
Sensitivity analysis on causal events of WIP bubbles by a log-driven simulator
Proceedings of the 39th conference on Winter simulation: 40 years! The best is yet to come
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Semiconductor wafer fabrication is perhaps one of the most complex manufacturing processes found today. In this paper, we construct a simulation model of part of a wafer fab using ProModel® software and analyze the effect of different input variables on selected parameters, such as cycle time, WIP level and equipment utilization rates. These input variables include arrival distribution, batch size, downtime pattern and lot release control. SEMATECH DATASET which has the original actual wafer fab data is used for our analysis.