Introduction to operations research, 4th ed.
Introduction to operations research, 4th ed.
Architecture and bus-arbitration schemes for MPEG-2 video decoder
IEEE Transactions on Circuits and Systems for Video Technology
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This paper presents a methodology of decision-making for embedded I/O buffer sizes in a single-bus shared-memory system. The decision is made with the aid of a queuing model, simulation, and the proposed algorithm. The generalized queueing model is simulated to cover two cases: independent processing units and pipelined processing units in a shared-memory environment. The objective is to obtain the best performance with the optimized embedded buffers in the system. Therefore, an algorithm is developed to find the optimal solution efficiently by exploring the correlation between buffers and system performance. The local optimum is guaranteed. The method can be widely applied to many applications.