On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes

  • Authors:

  • Yanni Chen;Keshab K. Parhi

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Minnesota, 4-174 EE/Csci Building, 200 Union Street S.E., Minneapolis, MN 55455, USA;Department of Electrical and Computer Engineering, University of Minnesota, 4-174 EE/Csci Building, 200 Union Street S.E., Minneapolis, MN 55455, USA

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2005

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this paper, both performance and complexity aspects of two-dimensional single parity check turbo product codes (I-SPC-TPC) are investigated. Based on the proposed I-SPC-TPC coding scheme, a parallel decoding structure is developed to increase the decoding throughput with minor performance degradation compared with the serial structure. For both decoding architectures, a new helical interleaver is constructed to further improve the coding gain. In terms of decoding algorithm, the extremely simple Sign-Min decoding is alternatively derived with only three additions needed to compute each bit's extrinsic information. For performance evaluation, (16, 14, 2)2 single parity check turbo product code with code rate 0.766 over AWGN channel using QPSK modulation is considered. The simulation results using Sign-Min decoding show that it can achieve bit-error-rate of 10−5 at signal-to-noise ratio of 3.8 dB with 8 iterations. Compared to the same rate and codeword length turbo product code composed of extended Hamming codes, the considered scheme can achieve similar performance with much less complexity. Important implementation issues such as the finite precision analysis, efficient sorting circuit design and interleaver memory management are also presented.