Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2

Authors:
Grigorios Magklis;Jose Gonzalez;Antonio Gonzalez
Affiliations:
Intel Barcelona Research Center;Intel Barcelona Research Center;Intel Barcelona Research Center
Venue:
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Year:
2004

Citing 0
Cited 4

Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture

Proceedings of the 2006 international symposium on Low power electronics and design
Meeting points: using thread criticality to adapt multicore hardware to parallel regions

Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors

ACM Transactions on Architecture and Code Optimization (TACO)
Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and Globally Asynchronous Locally Synchronous (GALS) designs. We also present a mechanism for dynamically adapting the frequency and voltage of the frontend of the CMCD with the goal to optimize the energy-delay^2 product (ED2P). Our mechanism has minimal hardware cost, is entirely self-adjustable, does not depend on any thresholds, and achieves results close to optimal. We evaluate it on 16 SPEC 2000 applications and report 17.5% ED2P reduction on average (80% of the upper bound).