A quantitative analysis of the performance impact of specialized bytecodes in java

  • Authors:

  • Ben Stephenson;Wade Holst

  • Affiliations:

  • University of Western Ontario, London, Ontario, Canada;University of Western Ontario, London, Ontario, Canada

  • Venue:
  • CASCON '04 Proceedings of the 2004 conference of the Centre for Advanced Studies on Collaborative research
  • Year:
  • 2004

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Abstract

Java is implemented by 201 bytecodes that serve the same purpose as assembler instructions while providing object-file platform independence. A collection of core bytecodes provide critical and independent functionality while a collection of specialized bytecodes is meant to improve on the performance of some of the core bytecodes. This study identifies 67 specialized bytecodes and shows the impact of their removal by despecializing them into semantically equivalent core bytecodes. A detailed analysis of the effects of despecialization on execution efficiency and class-file size was performed. The effects on the SPEC JVM98 Benchmark Suite were analyzed for various subsets of the despecialized bytecodes using three distinct Java virtual machines. When all 67 bytecodes were despecialized, the average slow down across all benchmarks and virtual machines was 2.1 percent, while the single largest performance loss for any one benchmark was 12.7 percent. In some cases, a speedup was observed. An analysis of the impact of despecialization on class file size was also conducted. It was found that the average class file size increased by approximately 6 percent when 67 specialized bytecodes were removed. This study shows that many of the specialized bytecodes currently in use offer little benefit to either execution efficiency or class file size. Thus, they can be considered as candidates for removal to make room for new bytecodes that will allow for the efficient implementation of new language features, offer significant performance gains or meaningfully reduce class file sizes. Furthermore, these results should be considered by designers who are developing new instruction sets for both virtual machines and hardware processors.