A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits

  • Authors:
  • Shiy Xu;E. Edirisuriya

  • Affiliations:
  • Shanghai University;University of Sri Jayewardenepura

  • Venue:
  • ATS '04 Proceedings of the 13th Asian Test Symposium
  • Year:
  • 2004

Quantified Score

Hi-index 0.00

Visualization

Abstract

Reconvergent fanout has been one of the critical issues for testing of VLSI circuits and design for testability. In this paper we will present a new algorithm, which will detect all sources of reconvergent fanout branch pairs by processing a normal circuit description. The algorithm identifies all the gates at which reconvergence occurs, the reconvergent sites, and lists all the reconvergent fanout branch pairs that are reconvergent at these sites. The automatic detection of such reconvergence can be used for improving the testability analysis or assist test generation of circuits containing such fanout branches.