Minimizing total weighted tardiness on a single batch process machine with incompatible job families

Authors:
Imelda C. Perez;John W. Fowler;W. Matthew Carlyle
Affiliations:
Motorola Corp.;Arizona State University, Tempe, AZ;Arizona State University
Venue:
Computers and Operations Research
Year:
2005

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Abstract

The diffusion step in semiconductor wafer fabrication is very time consuming, compared to other steps in the process, and performance in this area has a significant impact on overall factory performance. Diffusion furnaces are able to process multiple lots of similar wafers at a time, and are therefore appropriately modeled as batch processing machines with incompatible job families. Due to the importance of on-time delivery in semiconductor manufacturing, we focus on minimizing the total weighted tardiness in this environment. The resulting problem is NP-Hard, and we decompose it into two sequential decision problems: assigning lots to batches followed by sequencing the batches. We develop several heuristics for these subproblems and test their performance.