Simulating a pipelined floating point adder with MPI

  • Authors:
  • John H. Reynolds

  • Affiliations:
  • Mary Washington College, Fredericksburg, VA

  • Venue:
  • Journal of Computing Sciences in Colleges
  • Year:
  • 2004

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Abstract

This paper describes a simulation that applies the low-level techniques used to accomplish floating point addition. The various stages are identified with emphasis placed on bit-level implementations representing steps like adjusting biased exponents and normalizing. Once the sequential adder is established, the simulation is extended by applying parallelism to pipeline the stages so that many additions can occur in an assembly line fashion.