Reducing the Soft-Error Rate of a High-Performance Microprocessor

Authors:
Christopher T. Weaver;Joel Emer;Shubhendu S. Mukherjee;Steven K. Reinhardt
Affiliations:
Intel;Intel;Intel;University of Michigan
Venue:
IEEE Micro
Year:
2004

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Abstract

Unlike traditional approaches, which focus on detecting and recovering from faults, the techniques introducedhere reduce theprobability that a fault will cause a declared error. the first approach reduces the time instructions sit in vulnerable storage structures. The second avoids declaring errors on benign faults. Applying these techniques to a microprocessor instruction queue significantly reduces its error rate with only minor performance degradation.