Evaluation of Speed and Area of Clustered VLIW Processors

• Authors: Andrei Terechko;Manish Garg;Henk Corporaal
• Venue: VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
• Year: 2005

Splitting a wide-issue VLIW processor in clusters decreases the clock period, area and power consumption. Previous studies of the physical benefits from clustering focused on the scalability of the register file, based on speculative analytical models. In contrast, we evaluate speed and area of the whole VLIW datapath, including the register files, FUs, and bypasses through realistic physical layout experiments. Our baseline is an optimized for speed 8-issue-slot VLIW pipeline, derived from a commercial media processor. Despite the frequent prior-art assumption that the register file defines the clock frequency of a clustered VLIW processor, we discovered it is the FU bypass network that limits the clock speed. After a drastic 1.75 clock frequency speedup from clustering the unicluster into two clusters, subsequent clustering brings modest 2.05 and 2.17 speedups for the 4- and 8-cluster VLIWs, respectively. Combined with cycle count increase trends due to clustering, this leads to the conclusion that excessive clustering does not speed up the processor. Furthermore, clustering reduces area of the VLIW datapath. In our experiments the area savings due to clustering reach 14.2%, 43.5% and 50.5% for the 2-, 4-, and 8-cluster VLIWs, respectively.