On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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To realize energy-efficient buses in current nanometer-scale technologies, techniques like compression or encoding that exploit information redundancy have been explored. However, available compression techniques for buses do not always ensure energy-efficient transmission of compressed information. In this work, we present various techniques that can be used with compression schemes for buses to ensure high energy efficiency. Our best scheme, applied to a stream of 38-bit addresses issued in a typical microprocessor, yields about 14.7% energy reduction on the average across a wide range of compressed bus widths ranging and over many SPEC CPU2000 benchmarks. Our proposed techniques especially perform better 驴 up to 28.8% energy reduction is obtained 驴 for narrower bus widths in the range 8-16 bits.