Open issues and challenges in providing quality of service guarantees in high-speed networks
ACM SIGCOMM Computer Communication Review
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A framework for guaranteeing statistical QoS
IEEE/ACM Transactions on Networking (TON)
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
Networks on chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Introducing the SuperGT network-on-chip: SuperGT QoS: more than just GT
Proceedings of the 44th annual Design Automation Conference
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
An analytical model of broadcast in QoS-aware wormhole-routed NoCs
Journal of Systems and Software
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs
Journal of Parallel and Distributed Computing
Dynamic QoS management for chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks
Journal of Parallel and Distributed Computing
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Microprocessors & Microsystems
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As Moore's Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completing designs. In particular, the system interconnect must efficiently service a diverse set of data flows with widely ranging quality-of-service (QoS) requirements. However, the known solutions foroff-chip interconnects such as large-scale networks are not necessarily applicable to the on-chip environment. Latency and memory constraints for on-chip interconnects are quite different from larger-scale interconnects. This paper introduces a novel on-chip interconnect arbitration scheme. We show how this scheme can be distributed across a chip for high-speed implementation. We compare the performance of the arbitration scheme with other known interconnect arbitration schemes. Existing schemes typically focus heavily on either lowlatency of service for some initiators, or alternatively on guaranteed bandwidth delivery for other initiators. Our scheme allows service latency on some initiators to be traded off smoothly against jitter bounds on other initiators, while still delivering bandwidth guarantees. This scheme is a subset of the QoS controls that are available in the SonicsMX驴 (SMX) product.