Parallel-beam backprojection: an FPGA implementation optimized for medical imaging
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
An FPGA-Based Fan Beam Image Reconstruction Module
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Hardware for Tomographic Processing
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
A quantitative analysis of the speedup factors of FPGAs over processors
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
O(N2log2N) filtered backprojection reconstruction algorithm for tomography
IEEE Transactions on Image Processing
Hardware/software 2D-3D backprojection on a SoPC platform
Proceedings of the 2006 ACM symposium on Applied computing
High speed 3D tomography on CPU, GPU, and FPGA
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
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Medical image processing in general and computerized tomography (CT) in particular can benefit greatly from hardware acceleration. This application domain is marked by computationally intensive algorithms requiring the rapid processing of large amounts of data. To date, reconfigurable hardware has not been applied to the important area of image reconstruction. For efficient implementation and maximum speedup, fixed-point implementations are required. The associated quantization errors must be carefully balanced against the requirements of the medical community. Specifically, care must be taken so that very little error is introduced compared to floating-point implementations and the visual quality of the images is not compromised. In this paper, we present an FPGA implementation of the parallel-beam backprojection algorithm used in CT for which all of these requirements are met. We explore a number of quantization issues arising in backprojection and concentrate on minimizing error while maximizing efficiency. Our implementation shows approximately 100 times speedup over software versions of the same algorithm running on a 1 GHz Pentium, and is more flexible than an ASIC implementation. Our FPGA implementation can easily be adapted to both medical sensors with different dynamic ranges as well as tomographic scanners employed in a wider range of application areas including nondestructive evaluation and baggage inspection in airport terminals.