Journal of Parallel and Distributed Computing
MPI: The Complete Reference
Parallel Architectures and Parallel Algorithms for Integrated Vision Systems
Parallel Architectures and Parallel Algorithms for Integrated Vision Systems
Optimal Processor Assignment for a Class of Pipelined Computations
IEEE Transactions on Parallel and Distributed Systems
Application of Parallel Processors to Real-Time Sensor Array Processing
IPPS '99/SPDP '99 Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing
Parallel algorithms for space-time adaptive processing
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
Issues in using heterogeneous HPC systems for embedded real time signal processing applications
RTCSA '95 Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications
Toward a Portable Parallel Library for Space-Time Adaptive Methods
Toward a Portable Parallel Library for Space-Time Adaptive Methods
Parallel pipelined computational model for space-time adaptive processing
Parallel pipelined computational model for space-time adaptive processing
Feedback-directed pipeline parallelism
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
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This paper presents further results on the design and implementation of various optimizations based on our earlier work of developing a parallel pipelined model for the computational intensive applications that have multiple processing tasks. Performance evaluation of this model was done by using a real-time airborne radar application that employs a Space-Time Adaptive Processing (STAP) algorithm. This paper focuses on the following four issues: (1) The tradeoffs between increasing the throughput and reducing the latency are examined in more detail when allocating processors among different processing tasks. (2) A multi-threaded design is incorporated into the pipeline model and implemented on a massively parallel computer with symmetric multi-processor nodes, which shows enhanced performance. (3) The disk I/O is incorporated into the parallel pipeline to study its effect on performance in which two I/O task designs have been implemented: embedding I/O in the pipeline or having a separate I/O task. By using a double buffering approach together with the asynchronous I/O, the overall pipeline performance scales well as the number of processors increases. (4) From the comparison of the two I/O implementations, it is discovered that the latency may be improved when merging multiple tasks into a single task. The effect of reorganizing the task structure of the pipeline is discussed in detail. All the performance results shown in this work demonstrate the linear scalability the parallel pipeline model can achieve using a production radar application. Although this paper focuses on the implementation of the parallel pipeline model and uses the results from a STAP application to support the claims of the discovered properties for this pipeline, this model is also applicable to many other types of applications with similar computational characteristics.